From 549b1965f86d5198b587b54255ce5f7691261b48 Mon Sep 17 00:00:00 2001
From: Timothy E Baldwin <T.E.Baldwin99@members.leeds.ac.uk>
Date: Sat, 2 Nov 2013 18:04:06 +0000
Subject: [PATCH 30/35] Modules 1 - Fileswitch

---
 .../RiscOS/Sources/FileSys/FileSwitch/s/FSControl  | 42 +++++++++++-----------
 .../RiscOS/Sources/FileSys/FileSwitch/s/FileSwBody |  4 +++
 2 files changed, 26 insertions(+), 20 deletions(-)

diff --git a/castle/RiscOS/Sources/FileSys/FileSwitch/s/FSControl b/castle/RiscOS/Sources/FileSys/FileSwitch/s/FSControl
index 73938d9..ce7eb60 100644
--- a/castle/RiscOS/Sources/FileSys/FileSwitch/s/FSControl
+++ b/castle/RiscOS/Sources/FileSys/FileSwitch/s/FSControl
@@ -429,7 +429,7 @@ Run_UndatedFile
 77
         MOV     sp, r10                 ; Flatten superstack, we don't return
 
-        WritePSRc 0, r12                ; USR mode, all ints on
+        SWI     OS_LeaveOS              ; USR mode
         MOV     r12, #&80000000         ; Cause address extinction if used
         MOV     r13, #&80000000         ; (keep 1.20 compat capable)
         ADR     lr, ReturnFromAbsoluteCode
@@ -465,14 +465,9 @@ Run_TransientFile
 ; r10-r12 assumed to be preserved by the main SWI handler.
 
         ASSERT  transient_savearea = 0 
-  [ SASTMhatbroken
-        STMIA   r2!,{r6-r9}
-        STMIA   r2, {r13,r14}^   ; Must preserve r13_usr and r14_usr
-        SUB     r2, r2, #4*4     ; r0-r5 already stacked
-  |
-        STMIA   r2, {r6-r9, r13-r14}^   ; Must preserve r13_usr and r14_usr
-                                        ; r0-r5 already stacked
-  ]
+        STMIA   r2, {r6-r9}             ; r0-r5 already stacked
+        ADD     r9, r2, #4*4            ; Setup for write below
+
         ; Load the code after the info block
         MOV     r0, #object_file
         ADD     r3, r2, #transient_code
@@ -498,7 +493,9 @@ Run_TransientFile
         LDR     r0, CommandLine
         LDR     r1, commandtailptr
 
-        WritePSRc 0, wp                 ; USR mode, all ints on
+        SWI     OS_LeaveOS              ; USR mode
+        STMIA   r9, {r13,r14}           ; Must preserve r13_usr and r14_usr
+
         ADD     r5, r3, r5              ; r12 -> transient workspace. Not bank
         SUB     wp, r5, #transient_code ; Must correct as r5 = info + code
                                         ; and r2 = code^
@@ -511,6 +508,7 @@ Run_TransientFile
 
 88      LDR     r0, globalerror         ; fp is valid, of course ...
         MOV     r1, #V_bit
+        BL      CopyErrorExternal
         B       DeleteTransient
 
 ; *****************************************************************************
@@ -570,22 +568,26 @@ ReturnFromPIC
 
         Pull    "fp, wp"                ; Sanity slowly restoring ...
 
-; .............................................................................
-; In    fp, wp valid
-;       r1 = psr
-;       r0 -> error block if r1 has V set
-
-DeleteTransient
-
-; Delink this block from the transient list now that it has returned
+        TST     r1, #V_bit              ; Did it report error ?
+        BLNE    CopyErrorExternal
 
 ; Restore saved registers from the block
 
         LDR     r2, TransientBlock
+ [ ParaVirt
+        GetVCpu
+        LDMIA   r2, {r6-r11}
+        STR     r10, [r0, #vcpu_r13_usr]
+        STR     r11, [r0, #vcpu_r14_usr]
+ |
         LDMIA   r2, {r6-r9, r13-r14}^   ; Writing to r13,r14_usr
+        NOP
+ ]
 
-        TST     r1, #V_bit              ; Did it report error ?
-        BLNE    CopyErrorExternal
+
+DeleteTransient
+
+; Delink this block from the transient list now that it has returned
 
         ADR     r0, TransientBlock
         BL      SFreeLinkedArea         ; Accumulates V
diff --git a/castle/RiscOS/Sources/FileSys/FileSwitch/s/FileSwBody b/castle/RiscOS/Sources/FileSys/FileSwitch/s/FileSwBody
index 3849be1..1e220d5 100644
--- a/castle/RiscOS/Sources/FileSys/FileSwitch/s/FileSwBody
+++ b/castle/RiscOS/Sources/FileSys/FileSwitch/s/FileSwBody
@@ -745,8 +745,12 @@ FileSwitch_ModFlags
 
 ; I can now just about survive RMTidy, I guess !
 
+        PVJumpTable
+
 FileSwitch_Init Entry "r7"
 
+        InitPVOps
+
         ; Macro to disallow rip-off RAM loaded version (te he ;-)
         ChkKernelVersion
 
-- 
1.8.4.rc3

